Contemporary very large scale integration (VLSI) technology commonly includes one or more communication circuits incorporated with standard logic functions in a single integrated circuit (IC) chip or functional module. Between ICs, data can be serially transmitted via a communication line using one of several conventional serial transmission techniques including: synchronous input/output (I/O) communication, UART (Universal Asynchronous Receiver/Transmitter), and I.sup.2 C communication.
In synchronous I/O communication, the transmitting and receiving functions are synchronized using an auxiliary signal, for example a clock. Each function includes a controller for effecting serial transmission. At least two communication lines are required (clock and data lines), along with an auxiliary control line for enabling/disabling the communication circuit.
UART technology is designed to operate in both transmit and receive directions. Eight data lines operate as a parallel interface for internal logic, and a fully-structured serial interface is provided for a serial communication line. The UART further includes a control block for enabling serial transmission.
The UART transmission technique suffers from relatively limited signal transmission speed. Furthermore, when the control block is incorporated in an IC module, it occupies a relatively large portion of the IC circuit area, and further generates electromagnetic interference (EMI) noise resulting from rapid toggling of data and clock signals. During serial communication, a parity bit is commonly inserted into a serial data frame as a data integrity check, and a complementary data signal may be transmitted with the original data to effect transmission verification at the receiver. Such verification techniques generally require a complicated circuit configuration in the communication circuit and signal transmission system.